This invention relates generally to a structure for configuring small-scale integrated circuits into a large scale integrated circuit and more particularly to the configuration of a plurality of semiconductor circuits, defined as unit circuits, formed in a semiconductor body to form a large scale functional integrated circuit. It is well known in the manufacture of integrated circuit bodies or wafers that as wafer size and complexity increase so also does the likelihood that manufacturing defects will be introduced and render the integrated circuit defective and inoperable. Various techniques for increasing the yield and reducing the likelihood of imperfect and malfunctioning circuits have been developed. One such technique known as discretionary wiring provides for the individual testing of circuits formed in the wafer, the mapping of functional circuits and the formation, by computer control, of a custom metallization mask, which then is used to form a unique metallization interconnecting layer connecting solely the functional sub-unit circuits. Key drawbacks of this technique are the cost of the computer processing of custom masks for each individual wafer in addition to the subsequent mask formation steps.
There is therefore a substantial need for a technique wherein a plurality of small scale semiconductor circuits or unit circuits may be formed in a semiconductor wafer. The functional circuits may then be segregated and thereafter easily and inexpensively configured or interconnected to form a large scale integrated circuit without the need for additional expensive processing steps.